Dyana: Hla-based Distributed Real-time Embedded Systems Simulation To

In this paper we present DYANA, an HLA-based hardware-in-the-loop simulation tool. This tool is used for distributed Real-Time Embedded Systems (RTES) simulation. RTES models are described by Unified Modeling Language (UML) statechart diagrams. The statechart diagram is transformed into HLA-based Simulation Model (HSM). After translation into HSM we use CERTI as the simulation runtime. The statechart diagram is also transformed into a Network of Timed Automata (NTA). After translation into NTA we use UPPAAL for RTES model verification. 1 DYANA OVERVIEW Development of embedded devices and of the RTES itself is a distributed process performed by several teams located in different organizations. The tool which support this process is needed. In this paper we present DYANA, a tool for simulation and verification of RTES. This tool is a new revision of DYANA simulation environment (Bakhmurov A. 1999). The key features of DYANA are: UML statecharts as the modeling language for RTES; unified notation for simulation and verification; Worst Case Execution Time (WCET) analysis using the Metamoc tool; OTF trace format for execution traces of models run in CERTI. Figure 1 shows the main components of DYANA: UML editor ArgoUML Verification tool UPPAAL Trace visualizer Vis4 UML to SCXML translator Federate code generator UML to UPPAAL translator Model tracer WCET tool METAMOC WCET computation